1. Field of the Invention
The present invention relates to a FRAM (Ferroelectric Random Access Memory), and more particularly, to a method of forming a ferroelectric memory cell having reduced line degradation.
2. Discussion of the Related Art
FRAM (ferroelectric random access memory) is a type of non-volatile read/write random access semiconductor memory. FRAM combines the advantages of SRAM (static random access memory), which has a fast writing speed, and EAROM (electrically alterable read-only memory), which are non-volatility and in-circuit programmability.
A ferroelectric memory cell consists of a ferroelectric capacitor and a transistor. The properties of a dielectric material in the FRAM provide special advantages. The dielectric material has a high dielectric constant and can be polarized by an electric field. The polarisation remains until it is reversed by an opposite electrical field. This makes the memory non-volatile.
In the FRAM integration process, the ferroelectric thin film can be damaged by some processes, such as top electrode etching, ferroelectric thin film etching and bottom electrode etching processes, resulting in severely degraded ferroelectric performance, especially concerning imprint performance.
Usually, a recovery annealing process in an oxygen atmosphere is applied after the bottom electrode etching process to eliminate damage received from the bottom electrode etching process. Similarly, after top electrode etching process, the ferroelectric thin film is annealed in an oxygen atmosphere to eliminate damage received from the top electrode etching process.
All these recovery annealing processes increase the complexity of FRAM integration process, and consequently increase the cost of FRAM device. In addition, the temperature for recovery annealing is difficult to chose. In the case where PLZT is used for the ferroelectric thin film, if the annealing temperature is too high, the Pb loss during the annealing causes degradation in the ferroelectric performance, especially in fatigue performance. If the annealing temperature is too low, the damage from the etching process may not be fully recovered so that the ferroelectric performance, especially the imprint performance, is affected. Also, the recovery annealing after each of the etching processes are usually carried out at temperatures lower than PLZT grain growth temperature. Therefore, these annealing processes will not change the grain structure much and there will be little vacancy diffusion generated during the annealing. The recovery from the damage caused by the etch process is consequently limited.
Accordingly, the present invention is directed to a ferroelectric memory cell that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a ferroelectric memory cell having improved ferroelectric performance.
Another object of the present invention is to provide a ferroelectric device having reduced line degradation.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.
In another aspect of the present invention, a method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and annealing the ferroelectric thin film layer for grain growth after forming the contact hole.
In another aspect of the present invention, a method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode, forming a top electrode layer on the ferroelectric thin film layer, etching the top electrode layer to form a top electrode, etching the ferroelectric thin film layer, etching the bottom electrode layer to form a bottom electrode, and co-annealing the ferroelectric thin film layer and the top electrode to recover from damages received from the etching processes.
In another aspect of the present invention, a method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, annealing the ferroelectric thin film layer for crystallization, forming a top electrode on the ferroelectric thin film layer, forming an encapsulation layer over the top electrode, etching the bottom electrode layer to form a bottom electrode, forming a dielectric layer on the encapsulation layer, forming a contact hole through the dielectric layer and the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.